High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)
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概要
- 論文の詳細を見る
This paper describes the hierarchical behavioral description language celled SFL and its processing system. This integrated CAD system called PARTHENON is used for designs of the leading ASICs in the NTT Systems Labs. This paper shows, therefore, the effectiveness of PARTHENON as a practical high-level synthesis system through real design experience. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follws: (1) It is not mixed with connection description, but employs only behavioral description (like procedual description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the real design of some leading ASICs at the NTT Systems Laboratories.
- 社団法人電子情報通信学会の論文
- 1993-09-25
著者
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Oguri K
Ntt Communications And Information Lab. Yokosuka‐shi Jpn
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Oguri Kiyoshi
Ntt Communications And Information Laboratories
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Nomura Ryo
Ntt Communication Science Laboratories
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Oguri Kiyoshi
Ntt Communication Science Laboratories
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Nagoya Akira
Ntt Communication Science Laboratories
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YUKISHITA Mitsuteru
NTT Communication Science Laboratories
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Nakamura Yukihiro
NTT Communication Science Laboratories
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Yukishita M
Ntt Communication Sci. Lab. Kyoto‐fu Jpn
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Nakamura Y
Ntt Communication Science Laboratories
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