Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution (Special Issue on Synthesis and Verification of Hardware Design)
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概要
- 論文の詳細を見る
This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FP-GAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.
- 社団法人電子情報通信学会の論文
- 1997-10-25
著者
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Nagoya Akira
Ntt Communication Science Laboratories
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Sawada Hiroshi
Ntt Communication Science Laboratories Ntt Corporation
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Suyama Takayuki
Ntt Communication Science Laboratories
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Sawada Hiroshi
Ntt Communication Science Laboratories
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