Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations

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概要

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• In this paper, we propose a transformation technique for the multiplications of one variable with multiple constants, which are frequently seen in the various applications of signal processing, image processing, and so forth. The method is based on the exploration of common subexpressions among constants and reduces the number of shifts, additions, and subtractions to implement linear computations with hardware. Our method searches for regularity among elements of a linear transform using matrix decomposition and generates a reduced dataflow graph which preserves the full regularity. We show experimental results obtained using Discrete Cosine Transform (DCT) and Fast Fourier Transform(FFT)and illustrate the effectiveness of the method.

• 社団法人電子情報通信学会の論文
• 1998-03-25

著者

• Nagoya Akira

  Ntt Communication Science Laboratories

• MATSUURA Akihiro

  NTT Communication Science Laboratories

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• Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution (Special Issue on Synthesis and Verification of Hardware Design)
• Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations

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