A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem (Special Section on VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subex-pressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.
- 社団法人電子情報通信学会の論文
- 1997-10-25
著者
-
NAGOYA Akira
NTT Network Innovation Laboratories, NTT Corporation
-
Matsuura A
Kyoto Univ. Kyoto‐shi Jpn
-
Nagoya A
Ntt Network Innovation Lab. Yokosuka‐shi Jpn
-
Nagoya Akira
Ntt Communication Science Laboratories
-
MATSUURA Akihiro
NTT Communication Science Laboratories
-
YUKISHITA Mitsuteru
NTT Communication Science Laboratories
関連論文
- Dynamically Reconfigurable Logic LSI : PCA-2(Recornfigurable Systems)(Reconfigurable Systems)
- Dynamically Reconfigurable Logic LSI : PCA-1 : The First Realization of the Plastic Cell Architecture
- A Method of Mapping Finite State Machine into PCA Plastic Parts(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem (Special Section on VLSI Design and CAD Algorithms)
- High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)
- An Architecture of a Specification Design Expert System
- A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
- Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications (Special Section on VLSI Design and CAD Algorithms)
- Restructuring Logic Representations with Simple Disjunctive Decompositions (Special Section on VLSI Design and CAD Algorithms)
- An Efficient Method for Finding an Optimal Bi-Decomposition (Special Section on VLSI Design and CAD Algorithms)
- Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution (Special Issue on Synthesis and Verification of Hardware Design)
- Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations
- Test Synthesis from Behavioral Description Based on Data Transfer Analysis : LETTER Special Issue on Synthesis and Verification of Hardware Design