Nagoya Akira | Ntt Communication Science Laboratories
スポンサーリンク
概要
関連著者
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Nagoya Akira
Ntt Communication Science Laboratories
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NAGOYA Akira
NTT Network Innovation Laboratories, NTT Corporation
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Nagoya A
Ntt Network Innovation Lab. Yokosuka‐shi Jpn
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Sawada Hiroshi
Ntt Communication Science Laboratories Ntt Corporation
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Sawada Hiroshi
Ntt Communication Science Laboratories
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Sawada H
Ntt Communication Sci. Lab. Kyoto Jpn
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Sawada Hiroshi
Department Of General Studies Nihon University
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Sawada H
Ntt Communication Sci. Lab. Kyoto‐fu Jpn
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YAMASHITA Shigeru
NTT Communication Science Laboratories
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Yamashita S
Department Of Electrical Engineering Osaka University
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MATSUURA Akihiro
NTT Communication Science Laboratories
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YUKISHITA Mitsuteru
NTT Communication Science Laboratories
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Oguri K
Ntt Communications And Information Lab. Yokosuka‐shi Jpn
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Oguri Kiyoshi
Ntt Communications And Information Laboratories
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Nomura Ryo
Ntt Communication Science Laboratories
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Oguri Kiyoshi
Ntt Communication Science Laboratories
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Matsuura A
Kyoto Univ. Kyoto‐shi Jpn
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Suyama Takayuki
Ntt Communication Science Laboratories
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Nakamura Yukihiro
NTT Communication Science Laboratories
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Yukishita M
Ntt Communication Sci. Lab. Kyoto‐fu Jpn
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Nakamura Y
Ntt Communication Science Laboratories
著作論文
- A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem (Special Section on VLSI Design and CAD Algorithms)
- High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)
- Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications (Special Section on VLSI Design and CAD Algorithms)
- Restructuring Logic Representations with Simple Disjunctive Decompositions (Special Section on VLSI Design and CAD Algorithms)
- An Efficient Method for Finding an Optimal Bi-Decomposition (Special Section on VLSI Design and CAD Algorithms)
- Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution (Special Issue on Synthesis and Verification of Hardware Design)
- Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations