Test Synthesis from Behavioral Description Based on Data Transfer Analysis : LETTER Special Issue on Synthesis and Verification of Hardware Design

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概要

• 論文の詳細を見る

• We developed a new test-synthesis that operates method based on data transfer analysis at the language level. Using this method, an efficient scan path is inserted to generate test data for the sequential circuit by using only a test generation tool for the combinatorial circuit. We have applied this method successfully to the behavior, logic, and test design of a 32-bit, RISC-type processor. The size of the synthesized circuit without test synthesis is 23,407 gates ; the size with test synthesis is 24,811 gates. This is an increase of only a little over 6%.

• 社団法人電子情報通信学会の論文
• 1995-03-25

著者

• Oguri Kiyoshi

  Ntt Communications And Information Laboratories

• Oguri Kiyoshi

  Ntt Communication Science Laboratories

• YUKISHITA Mitsuteru

  NTT Communication Science Laboratories

• Kawaoka Tsukasa

  NTT Communication Science Laboratories

関連論文

• A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem (Special Section on VLSI Design and CAD Algorithms)
• High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)
• An Architecture of a Specification Design Expert System
• Test Synthesis from Behavioral Description Based on Data Transfer Analysis : LETTER Special Issue on Synthesis and Verification of Hardware Design

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