An Architecture of a Specification Design Expert System
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概要
- 論文の詳細を見る
At the present stage of processor hardware design, design support technology for lower levels, such as layout design, has reached a practical state. We have studied and developed an upper level CAD system. We express those specifications in basic terms with object(or entity) descriptions for processes and data, and relation descriptions for the correlation between these entities. An expert system for computer architecture design has been implemented. With it, the designer Is able to use a specification description language in much the same way as a natural language. The system employs 293 rules to analyze the consistency and completeness of the specification. Finally, and RTL behavioral description can be synthesized from the original specification description through a process that employs 113 rules. We used the above expert system to perform the functional design of a simple pipeline processor which has 127 specification language lines. In this case, 212 SFL statements were generated by the system. In the simple processor, specification analyzing time is about 30 seconds, and synthesizing time is about 2 minutes.
- 一般社団法人情報処理学会の論文
- 1992-11-30
著者
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Oguri K
Ntt Communications And Information Lab. Yokosuka‐shi Jpn
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Oguri Kiyoshi
Ntt Communications And Information Laboratories
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Oguri Kiyoshi
Ntt Communication Science Laboratories
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YUKISHITA Mitsuteru
NTT Communication Science Laboratories
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Nakamura Yukihiro
NTT Communication Science Laboratories
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UCHIHASHI TOMOTAKA
NTT Network Information Systems Laboratories
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Yukishita M
Ntt Communication Sci. Lab. Kyoto‐fu Jpn
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Nakamura Y
Ntt Communication Science Laboratories
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- High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)
- An Architecture of a Specification Design Expert System
- Plastic Cell Architecture : A Scalable Device Architecture for General-Purpose Reconfigurable Computing(Special Issue on Novel VLSI Processor Architectures)
- Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
- Test Synthesis from Behavioral Description Based on Data Transfer Analysis : LETTER Special Issue on Synthesis and Verification of Hardware Design