CMOS Floating Gate Defect Detection Using Supply Current Test with DC Power Supply Superposed by AC Component(Fault Detection)(<Special Section>Test and Verification of VLSI)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

• 社団法人電子情報通信学会の論文
• 2004-03-01

著者

• HONDO Tsutomu

  Sharp Takaya Electronic Industry Co., Ltd.

• Hondo Tsutomu

  Sharp Takaya Electronics Industry Co. Ltd.

• Hondo Tsutomu

  Sharp Takaya Electronic Industry Co. Ltd.

• Okamoto T

  Faculty Of Engineering Okayama University Of Science

• Okamoto Takuji

  Faculty Of Engineering Okayama Univ.

• Yokohira Tokumi

  Faculty Of Engineering Okayama University

• Yokohira Tokumi

  Faculty Of Engineering Okayama Univ.

• Michinishi Hiroyuki

  Faculty of Engineering, Okayama University

• Kobayashi T

  Soc Division Renesas Technology Corporation

• KOBAYASHI Toshifumi

  SOC Division, Renesas Technology Corporation

• Michinishi Hiroyuki

  Faculty Of Engineering Okayama University Of Science

関連論文

• Testing for the Programming Circuit of SRAM-Based FPGAs
• Temperature Control and Packaging Optimization of the Integrated Hydrogen Sensor
• The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs
• Detection of CMOS Open Node Defects by Frequency Analysis(Dependable Computing)
• CMOS Floating Gate Defect Detection Using Supply Current Test with DC Power Supply Superposed by AC Component(Fault Detection)(Test and Verification of VLSI)
• Conversation Robot Participating in Group Conversation(Special Issue on the 2001 IEICE Excellent Paper Award)
• Node Placement Algorithms for Shuffle-Like Packet-Switched Networks with Wavelength-Division Multiplexing(The IEICE Transactions (publishedin Japanese) Vol. J 86-B, No.6(Communications))
• Minimum Test Set for Locally Exhaustive Testing of Multiple Output Combinational Circuits (Special Issue on VLSI Testing and Testable Design)

スポンサーリンク