PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs

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概要

• 論文の詳細を見る

• PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducing the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Suzuki Hisamitsu

  Nec Corporation

• Nakamura Kazuyuki

  NEC Corporation

• Kuhara Shigeru

  NEC Corporation

• Kimura Tohru

  NEC Corporation

• Takada Masahide

  NEC Corporation

• Yoshida Hiroshi

  NEC Corporation

• Yamazaki Tohru

  NEC Corporation

• Nakamura K

  Tokyo Inst. Technol. Tokyo Jpn

• Kimura T

  Components Division Oki Electric Industry Co. Ltd.

• Takada M

  Nec Corp. Kawasaki‐shi Jpn

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