A Cell Synthesis Method for Salicide Process Using Assignment Graph (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.
- 社団法人電子情報通信学会の論文
- 2000-12-25
著者
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Okada K
Communications Research Laboratory Ministry Of Posts And Telecommunications
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Okada K
The Design Technology Development Laboratory Ic Group Sharp Corporation
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Okada K
Kyoto Univ. Kyoto‐shi Jpn
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OKADA Kazuhisa
the Design Technology Development Laboratory, IC Group, Sharp Corporation
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YAMANOUCHI Takayuki
the Design Technology Development Laboratory, IC Group, Sharp Corporation
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KAMBE Takashi
the Design Technology Development Laboratory, IC Group, Sharp Corporation
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Okada K
Keio Univ. Yokohama‐shi Jpn
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Kambe T
Sharp Corp. Tenri‐shi Jpn
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Yamanouchi Takayuki
The Design Technology Development Laboratory Ic Group Sharp Corporation
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Okada Kazuhisa
The Department Af Anatomy School Of Medicine Kyoto University
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