Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure (Special Section on VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
- 社団法人電子情報通信学会の論文
- 2000-12-25
著者
-
KIMURA Shinji
the Graduate School of Information Science, Nara Institute of Science and Technology
-
Watanabe Katsumasa
The Graduate School Of Information Science Nara Institute Of Science And Technology
-
Matsunaga Y
Fujitsu Laboratories Ltd.
-
Matsunaga Yusuke
Fujitsu Laboratories Ltd.
-
Zhu Q
Hokkaido Univ. Sapporo‐shi Jpn
-
ZHU Qiang
the Graduate School of Information Science Nara Institute of Science and Technology
-
Matsunaga Yusuke
Fujitsu Laboratories Ltd
-
Kimura Shinji
The Graduate School Of Information Science Advanced Institute Of Science And Technology
-
Kimura Shinji
The Graduate School Of Information Science Nara Institute Of Science And Technology
関連論文
- Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis (Special Section on VLSI Design and CAD Algorithms)
- Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion (Special Section on VLSI Design and CAD Algorithms)
- Technology Mapping Technique for Increasing Throughput of Character Projection Lithography(Lithography-Related Techniques,Fundamentals and Applications of Advanced Semiconductor Devices)
- Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment (CAD, VLSI Design Technology in the Sub-100nm Era)
- Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems
- Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints(Test)(VLSI Design and CAD Algorithms)
- Phase Optimization in Technology Mapping
- Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design)
- Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure (Special Section on VLSI Design and CAD Algorithms)
- Preciseness of Discrete Time Verification (Special Section on VLSI Design and CAD Algorithms)
- An Iterative Improvement Method for State Minimization of Incompletely Specified Finite State Machines (Special Issue on Synthesis and Verification of Hardware Design)
- A New Algorithm for Boolean Matching Utilizing Structural Information : PAPER Special Issue on Synthesis and Verification of Hardware Design
- MINT-An Exact Algorithm for Finding Minimum Test Set (Special Section on VLSI Design and CAD Algorithms)
- Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
- Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability
- Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability
- Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability
- Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability