Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation

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概要

• 論文の詳細を見る
• 2012-08-01

著者

• Kimura Shinji

  The Graduate School Of Information Science Advanced Institute Of Science And Technology

• MAN Xin

  the Graduate School of Information, Production and Systems, Waseda University

• HORIYAMA Takashi

  the Graduate School of Science and Engineering, Saitama University

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• Preciseness of Discrete Time Verification (Special Section on VLSI Design and CAD Algorithms)
• Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
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