Preciseness of Discrete Time Verification (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1 / 2, and if the analysis result with a unit time u and that with a unit time u / 2 are the same, then u is the expected unit time.

• 社団法人電子情報通信学会の論文
• 1993-10-25

著者

• KIMURA Shinji

  the Graduate School of Information Science, Nara Institute of Science and Technology

• Haneda H

  Kobe Univ. Kobe‐shi Jpn

• Tsubota Shunsuke

  the Faculty of Engineering, Kobe University

• Haneda Hiromasa

  the Faculty of Engineering, Kobe University

• Tsubota Shunsuke

  The Faculty Of Engineering Kobe University

• Kimura Shinji

  The Graduate School Of Information Science Advanced Institute Of Science And Technology

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