Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design)

概要

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Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of back-tracks with reasonable computational time. And a fast test pattern generator featuring this unque sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.
社団法人電子情報通信学会の論文
1993-09-25