Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles (Special Section of Papers Selected from ITC-CSCC '98)
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概要
- 論文の詳細を見る
In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 μm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of ± and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level.As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.
- 社団法人電子情報通信学会の論文
- 1999-06-25
著者
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Park C‐y
Daegu Univ. Gyeongsan Kor
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Park Cheol-young
Department Of Endocrinology And Metabolism Kangbuk Samsung Hospital Sungkyunkwan University School O
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Nakajima Koji
Laboratory For Brainware Reseach Institute Of Electrical Comunication Tohoku University:laboratory F
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Nakajima Koji
Laboratory For Electronic Intelligent Systems Research Institute Of Electrical Communication Tohoku
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PARK Cheol-Young
Department of Computer and Communication Engineering, Taegu University
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