Implementation of Continuous-Time Dynamics on Stochastic Neurochip(<Special Section>Nonlinear Theory and its Applications)
スポンサーリンク
概要
- 論文の詳細を見る
The hardware implementation of a neural network model using stochastic logic has been able to integrate numerous neuron units on a chip. However, the limitation of applications occurred since the stochastic neurosystem could execute only discrete-time dynamics. We have contrived a neuron model with continuous-time dynamics by using stochastic calculations. In this paper, we propose the circuit design of a new neuron circuit, and show the fabricated neurochip comprising 64 neurons with experimental results. Furthermore, a new asynchronous updating method and a new activation function circuit are proposed. These improvements enhance the performance of the neurochip greatly.
- 社団法人電子情報通信学会の論文
- 2004-09-01
著者
-
SATO Shigeo
Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohok
-
Nakajima Koji
Laboratory For Brainware Reseach Institute Of Electrical Comunication Tohoku University:laboratory F
-
Nakajima Koji
Laboratory For Brainware Systems Laboratory For Nanoelectronics And Spintronics Research Institute O
-
AKIMOTO Shunsuke
Laboratory for Brainware Systems, Laboratory for Nanoelectronics and Spintronics, Research Institute
-
MOMOI Akiyoshi
Laboratory for Brainware Systems, Laboratory for Nanoelectronics and Spintronics, Research Institute
-
Sato Shigeo
Laboratory For Brainware Systems/nanoelectronics And Spintronics Research Institute Of Electrical Co
-
Momoi Akiyoshi
Laboratory For Brainware Systems Laboratory For Nanoelectronics And Spintronics Research Institute O
-
Akimoto Shunsuke
Laboratory For Brainware Systems Laboratory For Nanoelectronics And Spintronics Research Institute O
-
Sato Shigeo
Laboratory For Brainware Systems Laboratory For Nanoelectronics And Spintronics Research Institute O
-
Sato Shigeo
Laboratory for Brainware System, Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577 Japan
関連論文
- Retrieval Property of Associative Memory Based on Inverse Function Delayed Neural Networks(Nonlinear Problems)
- Design of a Neural Network Chip for the Burst ID Model with Ability of Burst Firing(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Dynamical Behavior of Neural Networks with Anti-Symmetrical Cyclic Connections(Oscillation, Dynamics and Chaos,Nonlinear Theory and its Applications)
- Recalling Temporal Sequences of Patterns Using Neurons with Hysteretic Property
- Temporal Sequences of Patterns with an Inverse Function Delayed Neural Network(Control, Neural Networks and Learning,Nonlinear Theory and its Applications)
- New Nonvolatile Analog Memories for Analog Data Processing
- New Nonvolatile Analog Memories for Building Associative Memories
- Magnetic Isolation on a Superconducting Ground Plane
- Numerical Investigation and Model Approximation for the Hysteretic Current-Voltage Characteristics of Josephson Junctions with Nonlinear Quasiparticle Resistance
- Single Electron Stochastic Neural Network(Nonlinear Theory and its Applications)
- Single Electron Random Number Generator(Electronic Circuits)
- Hardware Implementation of New Analog Memory for Neural Networks
- LSI Neural Chip of Pulse-Output Network with Programmable Synapse
- A Content-Addressable Memory Using "Switched Diffusion Analog Memory with Feedback Circuit" (Special Section on Analog Circuit Techniques and Related Topics)
- Switched Diffusion Analog Memory for Neural Networks with Hebbian Learning Function and Its Linear Operation (Special Section of Papers Selected from JTC-CSCC'95)
- Limit Cycles of One-Dimensional Neural Networks with the Cyclic Connection Matrix (Special Section of Papers Selected from JTC-CSCC'95)
- Superconducting neural circuits using stochastic logic and new fabrication process elements
- High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform
- Comparison between an AND Array and a Booth Encoder for Large-Scale Phase-Mode Multipliers(Special Issue on Superconductor Digital/Analog Circuit Technologies)
- Implementation of Continuous-Time Dynamics on Stochastic Neurochip(Nonlinear Theory and its Applications)
- Integrated Circuits of Map Chaos Generators (Special Section on Analog Circuit Techniques and Related Topics)
- Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles (Special Section of Papers Selected from ITC-CSCC '98)
- Digital Circuits Based on Single Flux Quanta
- Avoidance of the Permanent Oscillating State in the Inverse Function Delayed Neural Network(Neuron and Neural Networks,Nonlinear Theory and its Applications)
- Hardware Neural Network for a Visual Inspection System
- Hardware Implementation of a DBM Network with Non-monotonic Neurons
- Analysis of burst dynamics bound by potential with active areas
- Quantum Neural Network Composed of Kane's Qubits
- An Approach for Quantum Computing using Adiabatic Evolution Algorithm