Gate First PFET Poly-Si/TiN/Al_2O_3 Gate Stacks with Inversion Thicknesses Less than 15A for High Performance or Low Power CMOS Applications
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概要
- 論文の詳細を見る
- 2007-09-19
著者
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Linder B.
Ibm Semiconductor Research And Development Center
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NARAYANAN V.
IBM Semiconductor Research and Development Center
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PARUCHURI V.
IBM Semiconductor Research and Development Center
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CARTIER E.
IBM Semiconductor Research and Development Center
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KANAKASABAPATHY S.
IBM Semiconductor Research and Development Center
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Paruchuri V.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Narayanan V.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
関連論文
- Gate First PFET Poly-Si/TiN/Al_2O_3 Gate Stacks with Inversion Thicknesses Less than 15A for High Performance or Low Power CMOS Applications
- Reliability Issues in High-k Stacks
- Towards metal gate/high-k dielectric integration for high performance CMOS technology
- A Study of NBTI and PBTI (Charge Trapping) in High k Stacks with NiSi, TiN, Re Gates
- High-K/Metal Gate MOSFETsにおける新しいレイアウト依存性(IEDM特集(先端CMOSデバイス・プロセス技術))