NARAYANAN V. | IBM Semiconductor Research and Development Center
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概要
関連著者
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NARAYANAN V.
IBM Semiconductor Research and Development Center
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Paruchuri V.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Narayanan V.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Linder B.
Ibm Semiconductor Research And Development Center
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PARUCHURI V.
IBM Semiconductor Research and Development Center
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CARTIER E.
IBM Semiconductor Research and Development Center
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KANAKASABAPATHY S.
IBM Semiconductor Research and Development Center
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ZAFAR S.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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KIM Y.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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DORIS B.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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CALLEGARI A.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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STATHIS J.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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NING T.
IBM Semiconductor Research & Development Center (SRDC), Research Division, T. J. Watson Research Cen
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Callegari A.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Kim Y.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Zafar S.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Stathis J.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
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Ning T.
Ibm Semiconductor Research & Development Center (srdc) Research Division T. J. Watson Research C
著作論文
- Gate First PFET Poly-Si/TiN/Al_2O_3 Gate Stacks with Inversion Thicknesses Less than 15A for High Performance or Low Power CMOS Applications
- A Study of NBTI and PBTI (Charge Trapping) in High k Stacks with NiSi, TiN, Re Gates