Suppression of Gate Depletion in p^+-Polysilicon-Gated Sub-40nm pMOSFETs by Laser Thermal Processing

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Realization of Low CoSi_2/p^+-Silicon Contact Resistance with Low Junction Leakage Current and Junction Capacitance Using Laser Thermal Process
Suppression of Gate Depletion in p^+-Polysilicon-Gated Sub-40nm pMOSFETs by Laser Thermal Processing
A Novel Laser Annealing Process for Advanced CMOS with Suppressed Gate Depletion and Ultra-shallow Junctions
Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

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