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VLSI Design and Education Center (VDEC), The University of Tokyo | 論文
- Reducing scheduling overheads in dynamically reconfigurable processors (リコンフィギャラブルシステム)
- The AMS Extension to System Level Design Language-SpecC(System Level Design,VLSI Design and CAD Algorithms)
- Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks
- LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
- Reducing scheduling overheads in Dynamically Reconfigurable Processors
- Reducing scheduling overheads in Dynamically Reconfigurable Processors
- Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
- Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
- Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
- Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
- A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate(Special Section on Papers Selected from ITC-CSCC 2000)
- Multi-Level Bounded Model Checking with Symbolic Counterexamples
- A Unified Framework for Equivalence Verification of Datapath Oriented Applications
- An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences(Simulation and Verification, VLSI Design and CAD Algorithms)
- A Basic Framework for Event-Based Monitoring by Networked Smart Image Sensors (特集 画像の認識と理解)
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging