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VLSI Design and Education Center (VDEC), The University of Tokyo | 論文
- Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
- Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture
- Performance Estimation with Automatic False-Path Detection for System-Level Designs
- On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
- Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability
- Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands
- Trends in Formal Verification Techniques for C-based Hardware Designs
- High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
- C-12-40 Effect of CMOS Device Scaling on Time-domain Voltage-domain Dynamic Range
- A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing