A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate(Special Section on Papers Selected from ITC-CSCC 2000)

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概要

• 論文の詳細を見る

• In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed(or through-put). Examples are given comparing the proposed realization with the distributed arithmetic(DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.

• 社団法人電子情報通信学会の論文
• 2001-06-01

著者

• SAKUNKONCHAK Thanyapat

  VLSI Design and Education Center (VDEC), The University of Tokyo

• Sakunkonchak Thanyapat

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Sakunkonchak Thanyapat

  The Electrical Engineering Program Sirindhorn International Institute Of Technology Thammasat Univer

• TANTARATANA Sawasd

  the Electrical Engineering Program, Sirindhorn International Institute of Technology, Thammasat Univ

• Tantaratana S

  Thammasat Univ. Pathumthani Tha

関連論文

• Synchronization Verification in System-Level Design with ILP Solvers(System Level Design,VLSI Design and CAD Algorithms)
• Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
• A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate(Special Section on Papers Selected from ITC-CSCC 2000)

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