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VLSI Design and Education Center (VDEC), The University of Tokyo | 論文
- A 8bit two stage time-to-digital converter using time difference amplifier
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Performance-Constrained Transistor Sizing for Different Cell Count Minimization
- AI-1-4 超ディペンダブルVLSIへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
- Synchronization Verification in System-Level Design with ILP Solvers(System Level Design,VLSI Design and CAD Algorithms)
- EFSM-based Weight-oriented Concolic Testing for Embedded Software
- Multi-Level Bounded Model Checking with Symbolic Counterexamples
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications(Low Power Methodology, VLSI Design and CAD Algorithms)
- Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
- Reducing scheduling overheads in dynamically reconfigurable processors (VLSI設計技術)
- Reducing scheduling overheads in dynamically reconfigurable processors (コンピュータシステム)