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System LSI Laboratory, Mitsubishi Electric Corporation | 論文
- A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
- A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
- Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
- A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
- A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs (Special Issue on New Architecture LSIs)
- A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI
- A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
- 3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
- A 10-b 50 MS/s 500-mW A/D Converter Using a Differential-Voltage Subconverter (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- An Efficient Self-Timed Queue Architecture for ATM Switch LSIs (Special Issue on Multimedia, Analog and Processing LSIs)
- High-Speed 0.5μm SOI 1/8 Frequency Divider with Body-Fixed Structure for Wide Range of Applications