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Semiconductor and Integrated circuits Division, Hitachi, Ltd. | 論文
- A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
- Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells
- Large 1/f Noise in Polysilicon TFT Loads and Its Effects on the Stability of SRAM Cells
- Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
- Half-V_ltCCgt Plate Nonvolatile DRAMs with Ferroelectric Capacitors
- Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip(Microelectronic Test Structures)
- Influence of Doping Impurities on Stacking Fault Generation in Thermally Oxidized Silicon
- Dislocations and Tungsten Concerntration Profiles in Tungsten-Silicon Contact Areas
- A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits (Special Issue on ULSI Memory Technology)
- Effect of Oxide Charge Density in Passivation Films on Breakdown Voltage of Planar Diodes
- Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells