スポンサーリンク
Renesas Device Design | 論文
- A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
- Large 1/f Noise in Polysilicon TFT Loads and Its Effects on the Stability of SRAM Cells
- A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
- Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
- Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
- A CMOS Stochastic Associative Processor Using PWM Chaotic Signals(Special Issue on Integrated Systems with New Concepts)
- A Stochastic Association Circuit Using PWM Chaotic Signals
- A Stochastic Associative Memory Using Single-Electron Devices and Its Application in Digit Pattern Association
- Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core(Low-Power System LSI, IP and Related Technologies)
- Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
- A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))