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Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci | 論文
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
- An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
- Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
- Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
- Abnormal Oxidation of Nickel Silicide on N-Type Substrate and Effect of Preamorphization Implantation
- Low Temperature Formation of Highly Thermal Immune Ni Germanosilicide Using NiPt Alloy with Co Over-layer in Si_Ge_x according to Different Ge Fractions (x)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)