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Inter-University Semiconductor Research Center, Seoul National University | 論文
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
- Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
- Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
- Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
- Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme