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Institute Of Microelectronics National Cheng Kung University | 論文
- Two-Step Etching Mechanism of Ag-Si Nanostructure with Various Ag Nanoshape Depositions
- Efficient Improvement on Device Performance for sub-90nm CMOSFETs
- An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process
- Stress Technology Impact on Device Performances and Reliability for Sub-90nm Silicon-on-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (Special Issue: Solid State Devices & Materials)
- Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application
- Mobility Modulation Technology Impact on Device Performance and Reliability for sub-90nm SOI CMOSFETs
- The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs
- Width Effect on Hot-Carrier-Induced Degradation for 90nm Partially Depleted SOI CMOSFETs
- Width Effect on Hot-Carrier-induced Degradation for 90nm Partially Depleted SOI CMOSFET
- The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs
- Extra bonus on transistor optimization with stress enhanced notched-gate technology for sub-90nm complementary metal oxide semiconductor field effect transistor (Special issue: Solid state devices and materials)
- Efficient mobility enhancement engineering on 65nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process (Special issue: Solid state devices and materials)
- Investigation and Modeling of Stress Interactions on 90nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches (Special Issue: Solid State Devices & Materials)
- The Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-MOSFETs
- Impacts of Layout Dimensions and Ambient Temperatures on Silicon Based On-Chip RF Interconnects
- Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process
- Extra Bonus on Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET
- The Bias-Crystallization Mechanism on Structural Characteristics and Electrical Properties of Zn-In-Sn-O Film
- Narrow Width and Length Dependence of SiGe and Sallow-Trench-Isolation Stress Induced Defects in 45 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Strained SiGe Source/Drain
- Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors