Extra Bonus on Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET
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概要
- 論文の詳細を見る
- 2007-09-19
著者
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Lin C.-t.
United Microelectronics Corporation Central R&d Division
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Yeh W.-k.
Department Of Electrical Engineering National University Of Kaohsiung
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LAI C.-M.
Institute of Microelectronics, National Cheng Kung University
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FANG Y.-K.
Institute of Microelectronics, National Cheng Kung University
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HSU C.-W.
Department of Electrical Engineering, National University of Kaohsiung
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HSU C.-H.
United Microelectronics Corporation, Central R&D Division
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CHEN L.-W.
United Microelectronics Corporation, Central R&D Division
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HUANG Y.-T.
United Microelectronics Corporation, Central R&D Division
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TSAI C.-T.
United Microelectronics Corporation, Central R&D Division
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Hsu C.-w.
Department Of Electrical Engineering National University Of Kaohsiung
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Lai C.-m.
Institute Of Microelectronics National Cheng Kung University
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Hsu C.-h.
United Microelectronics Corporation Central R&d Division
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Chen L.-w.
United Microelectronics Corporation Central R&d Division
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Tsai C.-t.
United Microelectronics Corporation Central R&d Division
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Fang Y.-k.
Institute Of Microelectronics National Cheng Kung University
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Huang Y.-t.
United Microelectronics Corporation Central R&d Division