Horiguchi Naoto | IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

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著作論文

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications
W versus Co--Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes
Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology
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Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

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