Byun Jeong | Ulsi Laboratory Of Lg Semicon Co. Ltd.
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概要
関連著者
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Park J
Memory R&d Center Hyundai Electronics Industries Co. Ltd.
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Park Jin
R&d Division Lg Semicon. Co. Ltd.
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Byun J
Process Team R&d Division Lg Semicon.co.ltd.
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Byun Jeong
Ulsi Laboratory Of Lg Semicon Co. Ltd.
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Kim Jac
Microprocessing Research Lab. School Of Chemical Engineering College Of Engineering Seoul National U
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Park Jin
Advanced Process Team Memory R&d Division Hyundai Electronics Industries Co. Ltd.
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Park J
Yonsei Univ. Seoul Kor
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Park Jaehyuk
Department Of Electrical & Electronic Engineering. Toyohashi University Of Technology
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Park J
Hyundai Microelectronics Co. Ltd. Chungju Kor
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Lee Byung
Process Development Department 3 Memory R&d Division Hyundai Electronics Co. Ltd.
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Sohn D
Strategic Marheting. Applied Materials Korea
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Sohn Dong
Department Of Materials Science And Engineering Korea Advanced Institute Of Science And Technology
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Sohn Dong
R&d Division Lg Semicon. Co. Ltd.
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PARK Jin
ULSI Laboratory of LG Semicon Co., Ltd.
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KIM Jae
ULSI Laboratory of LG Semicon Co., Ltd.
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PARK Ji-Soo
Process Development Department 3, Memory R&D Division, Hyundai Electronics Co. Ltd.
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Byun Jeong
Process Team, R&D Division, LG Semicon.Co.Ltd.,
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Byun Jeong
Process Team R&d Division Lg Semicon.co.ltd.
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Sohn D
Applied Materials Korea Chungnam Kor
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PARK Jin
Process Team, Hyundai MicroElectronics Co., Ltd.
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KIM Jun
ULSI Laboratory of LG Semicon Co., Ltd.
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Sohn Dong
Process Team, R&D Division, LG Semicon.Co.Ltd.,
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Kim Jae
Process Team, R&D Division, LG Semicon.Co.Ltd.,
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Kim J
Hyundai Microelectronics Co. Ltd. Chungju Kor
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Kim J
Seoul National Univ. Seoul Kor
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Kim Jac
Process Team, R&D Division, LG Semicon.Co.Ltd.,
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SOHN Dong-Kyun
Process Gr., Adv. Tech. Lab., LG Semicon. Co. Ltd.
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LEE Byung
ULSI Laboratory of LG Semicon Co. Ltd.
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KIM Eui
ULSI Laboratory of LG Semicon Co. Ltd.
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HWANG Hyunsang
ULSI Laboratory of LG Semicon Co. Ltd.
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Hwang Hyunsang
Ulsi Laboratory Lg Semicon Co.
著作論文
- W as a Bit Line Interconnection in Capacitor-Over-Bit-line (COB) Structured Dynamic Random Access Memory (DRAM) and Feasible Diffusion Barrier Layer
- Reduction of junction leakage current and sheet resistance using C-49 TiSi_2 as a diffusion source
- Reduction of junction leakage current and sheet resistance using C-49 TiSi_2 as a diffusion source
- Formation of Low-Resistivity Gate Electrode Suitable for the Future Devices Using Clustered DCS-Wsix Polycide
- Structural Evaluation of CVD WSix and Its Effect on Polycide Line Resistance
- W as a BIT Line Interconnection in COB Structured DRAM and Feasible Diffusion Barrier Layer