BOEUF F. | STMicroelectronics

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著作論文

CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications
Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
Analytical model for subband engineering in undoped double gate MOSFETs
Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method
A Full Analytical Model to evaluate Strain Induced by CESL on MOSFET Performances
Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

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