LAVIRON C. | CEA-LETI

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著作論文

CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications
Highly Manufacturable and Cost-effective Single Ta_xC / Hf_xZr_O_2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond
Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

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