PAYET F. | STMicroelectronics
スポンサーリンク
概要
関連著者
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SKOTNICKI T.
STMicroelectronics
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BOEUF F.
STMicroelectronics
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SKOTNICKI T.
ST Microelectronics
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PAYET F.
STMicroelectronics
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MULLER M.
NXP Semiconductors
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MULLER M.
Philips Semiconductors
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POUYDEBASQUE A.
Philips
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Pouydebasque A.
Philips Semiconductor
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ORTOLLAND C.
Philips Semiconductor
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Ortolland C.
Philips Semiconductors
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LEVERD F.
STMicroelectronics
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LAVIRON C.
CEA-LETI
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JULLIAN S.
NXP Semiconductors
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MORIN P.
STMicroelectronics
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Hartmann J.
Cea-leti
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JULLIAN S.
Philips
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Bensahel D.
Nxp Semiconductors
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Perrot C.
Stmicroelectronics
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CASANOVA N.
STMicroelectronics
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CAMPIDELLI Y.
STMicroelectronics
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VILLANI N.
STMicroelectronics
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KERMARREC O.
STMicroelectronics
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EMONET N.
STMicroelectronics
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CARRON V.
CEA-LETI
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ARNAUD F.
STMicroelectronics
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BENSAHEL D.
STMicroelectronics
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SELLIER M.
STMicroelectronics
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DURIEZ B.
Philips Semiconductor
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JOSSE E.
STMicroelectronics
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BOROT B.
STMicroelectronics
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MONFRAY S.
STMicroelectronics
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SZCZAP M.
STMicroelectronics
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CAVASSILAS N.
L2MP
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MICHELINI F.
L2MP
著作論文
- Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
- A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method
- A Full Analytical Model to evaluate Strain Induced by CESL on MOSFET Performances