MULLER M. | Philips Semiconductors
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概要
関連著者
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SKOTNICKI T.
STMicroelectronics
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MULLER M.
NXP Semiconductors
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BOEUF F.
STMicroelectronics
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SKOTNICKI T.
ST Microelectronics
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MULLER M.
Philips Semiconductors
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PAYET F.
STMicroelectronics
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POUYDEBASQUE A.
Philips
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Pouydebasque A.
Philips Semiconductor
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DENORME S.
STMicroelectronics
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GOURAUD P.
STMicroelectronics
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BIDAL G.
NXP Semiconductors
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AIME D.
Freescale
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RAFIK M.
STMicroelectronics
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POKRANT S.
NXP Semiconductors
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KORMANN T.
NXP Semiconductors
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CHABANNE G.
Freescale
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BONNETIER S.
Freescale
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LAVIRON C.
CEA-LETI
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ZAUNER A.
NXP Semiconductors
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BIDAL G.
STMicroelectronics
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MONDOT A.
STMicroelectronics
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FENOUILLET-BERANGER C.
CEA-LETI
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AIME D.
STMicroelectronics
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KORMANN T.
Philips Semiconductors
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ZAUNER A.
Philips Semiconductors
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BRAECKELMANN G.
Freescale
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BARGE D.
Philips Semiconductors
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TOFFOLI A.
CEA-LETI
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TARNOWKA A.
Philips Semiconductors
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POKRANT S.
Philips Semiconductors
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Bensahel D.
Nxp Semiconductors
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SELLIER M.
STMicroelectronics
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DURIEZ B.
Philips Semiconductor
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JOSSE E.
STMicroelectronics
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BOROT B.
STMicroelectronics
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MONFRAY S.
STMicroelectronics
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ORTOLLAND C.
Philips Semiconductor
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Ortolland C.
Philips Semiconductors
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FENOUILLET-BERANGER C.
ST Microelectronics
著作論文
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications