Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond

スポンサーリンク

概要

• 論文の詳細を見る

• With continuous shrinkage of advanced ultralarge scale integrations (ULSI), the impact of line resistance on the devices has become more and more important. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier layer using Cu–Ti alloy seed to 45 nm node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2-nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-$k$ dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress migration performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2010-05-25

著者

• Koyu Asai

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Hiroshi Miyatake

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Hiroshi Miyatake

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Masao Mizuno

  Thin Film Section, Electronics Research Laboratory, KOBE STEEL, Ltd., Kobe 651-271, Japan

• Maekawa Kazuyoshi

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Ohmori Kazuyuki

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Mori Kenichi

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Kazuyuki Kohama

  Department of Materials Science and Engineering, Kyoto University, Sakyo-ku, Kyoto 606-8501, Japan

• Kazuhiro Ito

  Department of Materials Science and Engineering, Kyoto University, Sakyo-ku, Kyoto 606-8501, Japan

• Takashi Ohnishi

  Surface Design & Corrosion Research Section, Materials Research Laboratory, KOBE STEEL, Ltd., Kobe 651-271, Japan

• Masanori Murakami

  The Ritsumeikan Trust, Nakagyo-ku, Kyoto 604-8520, Japan

• Kazuyoshi Maekawa

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Maekawa Kazuyoshi

  Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

• Kenichi Mori

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Takashi Ohnishi

  Surface Design & Corrosion Research Section, Materials Research Laboratory, KOBE STEEL, Ltd., Kobe 651-271, Japan

• Kazuyuki Kohama

  Department of Materials Science and Engineering, Kyoto University, Kyoto 606-8501, Japan

• Masanori Murakami

  The Ritsumeikan Trust, Kyoto 604-8520, Japan

• Kazuyuki Ohmori

  Renesas Technology Corp., Hitachinaka, Ibaraki 312-8504, Japan

• Kazuhiro Ito

  Department of Materials Science and Engineering, Kyoto University, Kyoto 606-8501, Japan

• Mori Kenichi

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

関連論文

• Analytical Approach for Enhancement of n-Channel Metal--Oxide--Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing
• Cu Dual-Damascene Interconnects with Direct Chemical Mechanical Polishing Process on Porous Low-$k$ Film
• Characterizations of NiSi2-Whisker Defects in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with $\langle 110\rangle$ Channel on Si(100)
• Effects of Pore Sealing on Self-Formation of Ti-Rich Barrier Layers in Cu(Ti)/Porous-Low-$k$ Samples
• Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique
• Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films

スポンサーリンク