Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films

スポンサーリンク

概要

• 論文の詳細を見る

• In advanced LSI devices, the filling capability for the electroplating (ECP) process, impurities in Cu film, and grain growth after ECP are important properties of Cu interconnect reliability. It has been reported that the Cu grain growth depends on the ECP-Cu film characteristics and the annealing conditions. In this study, we focus on the deposition thickness of ECP-Cu films to control their microstructure. It is revealed that a thicker ECP-Cu film enlarges the Cu grain size and reduces the number of small grains. It is also revealed that Cu grains in a wide line with a thicker ECP-Cu film are larger, leading to reliability improvement. A film with larger grains has fewer grain boundaries and fewer diffusion paths of vacancies, and a film with fewer small grains has a decreased number of vacancies. As a result, stress-induced voiding phenomena are apparently suppressed by increasing the thickness of deposited ECP-Cu film.

• The Japan Society of Applied Physicsの論文
• 2013-05-25

著者

• Fujisawa Masahiko

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Maekawa Kazuyoshi

  Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

• Kudo Shuichi

  Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

• Mori Kenichi

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Suzumura Naohito

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Muranaka Seiji

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Shibata Ryuji

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Omori Kazuyuki

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

関連論文

• Analytical Approach for Enhancement of n-Channel Metal--Oxide--Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing
• Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance
• Characterizations of NiSi2-Whisker Defects in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with $\langle 110\rangle$ Channel on Si(100)
• Analysis of sidewall damage layer in low-k film using the interline dielectric capacitance measurements (Special issue: Advanced metallization for ULSI applications)
• Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain
• Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique
• Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films
• Stress Analysis for Chip–Package Interaction of Cu/Low-$k$ Multilayer Interconnects
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films

スポンサーリンク