Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

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概要

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• A fine-grained power-gating scheme combining metal–oxide–semiconductor (MOS) transistors with magnetic-tunnel-junction (MTJ) devices, where storage data still remains even if the power supply is cut off, is proposed for an ultra low-power bit-serial ternary content-addressable memory (TCAM). Once a mismatched result is detected in a sequence of a bit-level equality-search operation, the power supply of all the cells in the word circuit is cut off, which greatly reduces the standby power dissipation in the word circuit. The standby power dissipation of the proposed TCAM in the standby mode is reduced to about 1.2% in comparison with that of a complementary MOS (CMOS)-only-based TCAM. Moreover, the power-delay product of the proposed TCAM is reduced to 15.5% in comparison with that of the corresponding CMOS-only-based TCAM.

• 2010-04-25

著者

• Matsunaga Shoun

  Laboratory For Brainware Systems Research Institute Of Electrical Communication Tohoku University

• Hiyama Kimiyuki

  Laboratory For Brainware Systems Research Institute Of Electrical Communication Tohoku University

• Takahiro Hanyu

  Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Takahiro Hanyu

  Laboratory for Brainware Systems, Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Natsui Masanori

  Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Tetsuo Endoh

  Center for Interdisciplinary Research, Tohoku University, Sendai 980-8578, Japan

• Hideo Ohno

  Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Shoun Matsunaga

  Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Masanori Natsui

  Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

• Tetsuo Endoh

  Center for Interdisciplinary Research, Tohoku University, Aramaki aza Aoba 6-3, Aoba-ku, Sendai 980-8578, Japan

• Kimiyuki Hiyama

  Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan

関連論文

• Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices
• Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
• CoFeB Inserted Perpendicular Magnetic Tunnel Junctions with CoFe/Pd Multilayers for High Tunnel Magnetoresistance Ratio
• Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory
• The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits
• Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme
• Low Frequency Noise Characterization in Metal Oxide Semiconductor Field Effect Transistor Based Charge Transfer Device at Room and Low Temperatures

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