Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack
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概要
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We demonstrated an ideal scaling of inversion gate dielectric thickness ($T_{\text{inv}}$) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/μm at an off-leakage current of 50 nA/μm for the sub-30-nm n- and p-metal–oxide–semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the $T_{\text{inv}}$ scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter.
- 2010-04-25
著者
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FUKUTOME Hidenobu
Fujitsu Laboratories Ltd.
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Shigeo Satoh
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Kazuo Kawamura
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Hiroyuki Ohta
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Kazuya Okubo
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Yoichi Momiyama
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Okubo Kazuya
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Akiyama Shinichi
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Naoki Idani
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Hidenobu Fukutome
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Sinichi Akiyama
Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
関連論文
- Analysis of Non-Uniform Boron Penetration of Nitrided Oxide in PMOSFETs Considering Two-Dimensional Nitrogen Distribution
- Study of L_ dependence of 2-D carrier profile in N-FET by Scanning Tunneling Microscopy
- Direct measurement of the offset spacer effect on the carrier profiles in sub-50nm p-MOSFETs
- Characterization of Plasma Nitridation Impact on Lateral Extension Profile in 50 nm N-MOSFET by Scanning Tunneling Microscopy
- Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack
- Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy
- Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors