Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs
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概要
- 論文の詳細を見る
As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant ($k$) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-$k$ interconnects with via plugs.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-04-15
著者
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KAMEYAMA Akiko
NEC Electronics Corporation
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UENO Kazuyoshi
Advanced Device Development Division, NEC Electronics Corporation
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KAMEYAMA Akiko
Advanced Device Development Division, NEC Electronics Corporation
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MATSUMOTO Akira
Advanced Device Development Division, NEC Electronics Corporation
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IGUCHI Manabu
Advanced Device Development Division, NEC Electronics Corporation
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TAKEWAKI Toshiyuki
Advanced Device Development Division, NEC Electronics Corporation
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TOYOSHIMA Hironori
Advanced Device Development Division, NEC Electronics Corporation
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KAWAHARA Naoyoshi
Advanced Device Development Division, NEC Electronics Corporation
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SUZUKI Mieko
Advanced Device Development Division, NEC Electronics Corporation
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ODA Noriaki
Advanced Device Development Division, NEC Electronics Corporation
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Asada Susumu
Advanced Device Development Division Nec Electronics Corporation
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Oshida Daisuke
Advanced Device Development Division Nec Electronics Corporation
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Takewaki Toshiyuki
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Ueno Kazuyoshi
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Toyoshima Hironori
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Suzuki Mieko
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Asada Susumu
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Kameyama Akiko
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Oshida Daisuke
Advanced Device Development Division, NEC Electronics Corporation, Sagamihara, Kanagawa 229-1198, Japan
関連論文
- Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs
- A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13μm Complementary Metal Oxide Semiconductor Generation
- Suppression of Electromigration Early Failure of Cu/Porous Low-$k$ Interconnects Using Dummy Metal
- Electromigration Lifetime Enhancement of CoWP Capped Cu Interconnects by Thermal Treatment
- Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs