Topography Simulation for Nanometer Semiconductor Process

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概要

• 論文の詳細を見る

• In this paper, we propose a novel scheme for simulating the topography of nanometer semiconductor processes. Since the proposed scheme considers only the surface cells moving forward and backward during etching or deposition, the simulator does not suffer from an increased memory requirement due to the complexity of the high aspect-ratio structure built on the wafer. This method consists of steps for calculating the front surface moving forward and backward and converting the cell structure into a tetrahedral mesh structure for subsequent numerical simulation. This method mitigates the excessive memory requirement through a dynamic allocating scheme wherein only topographical data at the surface cell are taken into account. A spillover algorithm is also implemented in the simulator so that any excessive etching or deposition which is more than the rate acceptable at the exposed cell during a single time step is reconsidered in the adjacent cells. Our proposed scheme was verified for structures with complex geometry, such as a thin film transistor-liquid crystal display (TFT-LCD) structure, a read only memory (ROM) or a dynamic random access memory (DRAM) cell.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-04-30

著者

• Lee Jun-gu

  Department Of Electrical Engineering School Of Engineering Inha University

• Won Taeyoung

  Department Of Electrical Engineering National It Research Center For Computational Electronics Inha

• Lee Jun-Gu

  Department of Electrical Engineering, School of Engineering, Inha University, and National IT Research Center for Computational Electronics, 253 Yonghyun-dong, Nam-gu, Incheon, Korea 402-751

• Yoon Sukin

  Department of Electrical Engineering, School of Engineering, Inha University, and National IT Research Center for Computational Electronics, 253 Yonghyun-dong, Nam-gu, Incheon, Korea 402-751

• Won Taeyoung

  Department of Electrical Engineering, School of Engineering, Inha University, and National IT Research Center for Computational Electronics, 253 Yonghyun-dong, Nam-gu, Incheon, Korea 402-751

関連論文

• Fast and Accurate Simulation for Topography in Nanometer Semiconductor Process
• Two-Dimensional Quantum Mechanical Modeling of Strained-Si FinFETs on SiGe-On-Insulator(SGOI)
• Device Optimization of Multiple-Channel Field Effect Transistor with Two Dimensional Poisson–Schrödinger Solver
• Ab-initio Study on Energy Barrier for Neutral Indium Migration in a Silicon Substrate
• Atomistic Modeling of Boron Diffusion with Germanium Pre-amorphization for Ultra Shallow S/D Junction in nanometer-scale PMOS Devices
• Nanoscale Device Modeling and Simulation: Fin Field-Effect Transistor (FinFET)
• Kinetic Monte Carlo Modeling of Boron Diffusion in Strained Silicon
• Two-Dimensional Quantum-Mechanical Modeling and Simulation of Strained-Si Fin Field Effect Transistor (FinFET) on SiGe-On-Insulator
• Performance Comparison between Asymmetric Polycrystalline Silicon Gate and TiN Gate Fin-Shaped Field Effect Transistors
• Topography Simulation for Nanometer Semiconductor Process

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