Sub-100 nm Gate Technologies for Si/SiGe-Buried-Channel RF Devices
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概要
- 論文の詳細を見る
A novel fabrication process of sub-100 nm self-aligned T-gates for heterostructure field-effect transistors (HFETs) using optical contact lithography is presented. A 500-nm-wide polyimide fin is used as an implantation mask, shrunk by dry etching and subsequently replaced by a gate metal. A low-resistive gate head to form a T-shape is independently defined by wet chemical etching. Using this method, Si/SiGe modulation-doped field-effect transistors (MODFETs) have been prepared, having a gate length of 90 nm. The self-alignment enables the realization of very small source/gate and gate/drain spacings of 200 nm. This yields, together with an optimized salicide (self-aligned silicide) ohmic contact, a much lower access resistance compared to conventional gates defined by e-beam lithography. A record transit frequency $f_{\text{T}}$ of 90 GHz and a very high transconductance of 570 mS/mm have been achieved for MODFETs.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-15
著者
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Zeuner Marco
Daimlerchrysler Ag Research And Technology
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Kanel Hans
Laboratorium fur Festkorperphysik
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Hackbarth Thomas
Daimlerchrysler Ag Research And Technology
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Enciso-Aguilar Mauro
Institut d'Electronique Fondamentale, Paris-Sud University, 91405 Orsay, France
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Aniel Frederic
Institut d'Electronique Fondamentale, Paris-Sud University, 91405 Orsay, France
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Aniel Frederic
Institut d'Electronique Fondamentale, Paris-Sud University, 91405 Orsay, France
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Hackbarth Thomas
Daimler-Chrysler AG, Research Center Ulm, Wilhelm-Runge-St. 11, 89081 Ulm, Germany
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Hackbarth Thomas
DaimlerChrysler AG, Research and Technology, 89081 Ulm, Germany
関連論文
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- Fast Deposition Process for Graded SiGe Buffer Layers
- Low Frequency Noise in Insulated-Gate Strained-Si n-Channel Modulation Doped Field Effect Transistors
- Sub-100 nm Gate Technologies for Si/SiGe-Buried-Channel RF Devices
- Fast Deposition Process for Graded SiGe Buffer Layers
- Sub-100 nm Gate Technologies for Si/SiGe-Buried-Channel RF Devices