Trivalued Memory Circuit Using Metal–Oxide–Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process
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概要
- 論文の詳細を見る
A trivalued memory circuit based on two cascoded metal–oxide–semiconductor field-effect transistor bipolar-junction-transistor negative-differential-resistance (MOS-BJT-NDR) devices is investigated. The MOS-BJT-NDR device is made of MOS and BJT devices, but it can show the NDR current–voltage characteristic by suitably arranging the MOS parameters. We demonstrate a trivalued memory circuit using the two-peak MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35 μm SiGe process.
- Japan Society of Applied Physicsの論文
- 2006-09-25
著者
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Gan Kwang-jow
Department Of Electrical Engineering National Chiayi University
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LIANG Dong-Shong
Department of Electrical Engineering, National Cheng Kung University
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Tsai Cher-shiung
Department Of Electronic Engineering Kun Shan University
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Gan Kwang-Jow
Department of Electronic Engineering, Kun Shan University, 949 Da-Wan Road, Yung-Kang, Tainan Hsien 710, Taiwan, R.O.C.
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Wen Chun-Ming
Department of Electronic Engineering, Kun Shan University, 949 Da-Wan Road, Yung-Kang, Tainan Hsien 710, Taiwan, R.O.C.
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Chen Yaw-Hwang
Department of Electronic Engineering, Kun Shan University, 949 Da-Wan Road, Yung-Kang, Tainan Hsien 710, Taiwan, R.O.C.
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- Trivalued Memory Circuit Using Metal–Oxide–Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process
- Hysteresis Phenomena for the Series Circuit of Two Identical Negative Differential Resistance Devices