Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio

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概要

• 論文の詳細を見る

• The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.

• （社）電子情報通信学会の論文
• 2009-05-01

著者

• GAN Kwang-Jow

  Department of Electrical Engineering, National Cheng Kung University

• Tai Cheng-chi

  Department Of Electrical Engineering National Cheng Kung University

• Gan Kwang‐jow

  National Chiayi Univ. Twn

• Gan Kwang-jow

  Department Of Electrical Engineering National Chiayi University

• LIANG Dong-Shong

  Department of Electrical Engineering, National Cheng Kung University

• TSAI Cher-Shiung

  Department of Electronic Engineering, Kun Shan University

• Tsai Cher-shiung

  Department Of Electronic Engineering Kun Shan University

• Liang Dong‐shong

  Kun Shan Univ. Twn

関連論文

• Improved Circuit Design of Multipeak Current-Voltage Characteristics Based on Resonant Tunneling Diodes
• Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio
• Trivalued Memory Circuit Using Metal-Oxide-Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process
• Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit
• Characterization of Extrinsic Hysteresis Phenomena of Series-Connected Identical Esaki-Diode-Like Negative Differential Resistance Devices
• Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
• Thermal Dissipation of High-Brightness Light Emitting Diode by Using Multiwalled Carbon Nanotube/SiC Composites
• Investigation of the Combined Current–Voltage Characteristics of Two Similar Esaki-Diode-Like Devices
• Trivalued Memory Circuit Using Metal–Oxide–Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process
• Hysteresis Phenomena for the Series Circuit of Two Identical Negative Differential Resistance Devices

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