Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
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概要
- 論文の詳細を見る
The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.
- (社)電子情報通信学会の論文
- 2010-08-01
著者
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Gan Kwang-jow
Department Of Electrical Engineering National Chiayi University
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Chen Yan-wun
Department Of Electronic Engineering Kun Shan University
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LIANG Dong-Shong
Department of Electrical Engineering, National Cheng Kung University
関連論文
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- Characterization of Extrinsic Hysteresis Phenomena of Series-Connected Identical Esaki-Diode-Like Negative Differential Resistance Devices
- Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
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