A MASH 1-1-1 ΔΣ time-to-digital converter based on two-stage time quantization
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概要
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A MASH 1-1-1 ΔΣ time-to-digital converter (TDC), based on two-stage time quantization, was designed with a 0.13 μm CMOS process and a 1.2 V supply. A classical delay line and a Vernier delay line were used for coarse and fine quantization, respectively. Third-order noise-shaping was achieved using the proposed MASH 1-1-1 ΔΣ modulator. Simulation results showed that a resolution of up to 5.5 ps and a measurement range of 38.4 ns could be achieved. The proposed TDC consumes 4.9 mW and occupies 0.28 mm2.
著者
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Ji Xincun
National ASIC Center, Southeast University
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Wu Jianhui
National ASIC Center, Southeast University
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Wang Zixuan
National ASIC System Engineering Research Center, Southeast University
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Chen Qing
National ASIC System Engineering Research Center, Southeast University
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