A high-resolution stochastic time-to-digital converter with edge-interchange scheme

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概要

• 論文の詳細を見る

• A high-resolution stochastic time-to-digital converter (STDC) using an edge-interchange scheme is described. The proposed STDC provides a higher resolution but consumes less power than previous STDCs that gave the same resolution. The limitation on input phase difference caused by the arbiter and the edge-interchange circuit is analyzed. Simulated results show that for the task proposed herein, a resolution of up to 0.3ps is achieved while only 1.7mW is consumed. Furthermore, higher resolution is achieved, more power will be reduced by using the edge-interchange circuit.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Ji Xincun

  National ASIC Center, Southeast University

• Wu Jianhui

  National ASIC Center, Southeast University

• Wang Zixuan

  National ASIC System Engineering Research Center, Southeast University

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