A Low Power Test Pattern Generator for BIST
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概要
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To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.
著者
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LEI Shaochong
School of Electronic & Information Engineering, Xian Jiaotong University
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LIANG Feng
School of Electronic & Information Engineering, Xian Jiaotong University
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LIU Zeye
School of Electronic & Information Engineering, Xian Jiaotong University
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WANG Xiaoying
School of Electronic & Information Engineering, Xian Jiaotong University
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WANG Zhen
School of Electronic & Information Engineering, Xian Jiaotong University
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