An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07bits without calibration and 6.74bits with calibration up to 500MHz input signal at sampling rate of 600MSps. It dissipates 98.5mW on 1.2-V supply. FoM is 1.54pJ/conv.
著者
-
PAIK Daehwa
Department of Physical Electronics, Tokyo Institute of Technology
-
ASADA Yusuke
Advantest Corporation
-
MIYAHARA Masaya
Department of Physical Electronics, Tokyo Institute of Technology
-
MATSUZAWA Akira
Department of Physical Electronics, Tokyo Institute of Technology
関連論文
- An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques
- Analysis of CMOS Transconductance Amplifiers for Sampling Mixers
- A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter(Analog Circuits and Related SoC Integration Technologies)
- A Multi-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique
- A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling
- Evaluation of a Multi-Line De-Embedding Technique up to 110GHz for Millimeter-Wave CMOS Circuit Design
- Analysis of CMOS Transconductance Amplifiers for Sampling Mixers
- Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators
- Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators
- A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider
- The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
- An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques
- A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing
- The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time(Analog Circuits and Related SoC Integration Technologies)
- Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator
- A 0.5-V, 0.05-to-3.2GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition
- Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design